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version 2.109.1

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Enum core.simd.XMM

XMM opcodes that conform to the following:

enum XMM : int { ... }

opcode xmm1,xmm2/mem

and do not have side effects (i.e. do not write to memory).

Enum members

NameDescription
LODAPD MOVAPD xmm1, xmm2/m128
LODAPS MOVAPS xmm1, xmm2/m128
LODD MOVD xmm, reg/mem64 66 0F 6E /r
LODDQA MOVDQA xmm1, xmm2/m128
LODDQU MOVDQU xmm1, xmm2/mem128 F3 0F 6F /r
LODHPD MOVHPD xmm1, m64
LODHPS MOVHPS xmm1, m64
LODLPD MOVLPD xmm1, m64
LODLPS MOVLPS xmm1, m64
LODQ MOVQ xmm1, xmm2/m64
LODSD MOVSD xmm1, xmm2/m64
LODSS MOVSS xmm1, xmm2/m32
LODUPD MOVUPD xmm1, xmm2/m128
LODUPS MOVUPS xmm1, xmm2/m128
MOVDQ2Q MOVDQ2Q mmx, xmm F2 0F D6 /r
MOVHLPS MOVHLPS xmm1, xmm2 0F 12 /r
MOVLHPS MOVLHPS xmm1, xmm2
MOVMSKPD MOVMSKPD reg, xmm
MOVMSKPS MOVMSKPS reg, xmm
MOVNTDQ MOVNTDQ m128, xmm1
MOVNTI MOVNTI m32, r32
MOVNTPD MOVNTPD m128, xmm1
MOVNTPS MOVNTPS m128, xmm1
MOVNTQ MOVNTQ m64, mm
MOVQ2DQ MOVQ2DQ
STOAPD MOVAPD xmm2/m128, xmm1
STOAPS MOVAPS xmm2/m128, xmm1
STOD MOVD reg/mem64, xmm 66 0F 7E /r
STODQA MOVDQA xmm2/m128, xmm1
STODQU MOVDQU xmm1/mem128, xmm2 F3 0F 7F /r
STOHPD MOVHPD mem64, xmm1 66 0F 17 /r
STOHPS MOVHPS m64, xmm1
STOLPD MOVLPD m64, xmm1
STOLPS MOVLPS m64, xmm1
STOQ MOVQ xmm2/m64, xmm1
STOSD MOVSD xmm1/m64, xmm2
STOSS MOVSS xmm1/m32, xmm2
STOUPD MOVUPD xmm2/m128, xmm1
STOUPS MOVUPS xmm2/m128, xmm1

Example

float4 a;
a = cast(float4)__simd(XMM.PXOR, a, a);

Example

float4 a;
a = cast(float4)__simd(XMM.LODSS, a);

Example

float4 a;
a = cast(float4)__simd(XMM.CMPPD, a, a, 0x7A);

Example

float4 a;
a = cast(float4) __simd_ib(XMM.PSRLQ, a, 0x7A);

Example

void16 a;
float f = 1;
double d = 1;

cast(void)__simd_sto(XMM.STOUPS, a, a);
cast(void)__simd_sto(XMM.STOUPS, f, a);
cast(void)__simd_sto(XMM.STOUPS, d, a);

Authors

Walter Bright,

License

Boost License 1.0.