Menu
Search

API Documentation

version 2.111.0

overview

View source code
Display the source code in dmd/backend/arm/cod1.d from which thispage was generated on github.
Report a bug
If you spot a problem with this page, click here to create aBugzilla issue.
Improve this page
Quickly fork, edit online, and submit a pull request for this page.Requires a signed-in GitHub account. This works well for small changes.If you'd like to make larger changes you may want to consider usinglocal clone.

Function dmd.backend.arm.cod1.isscaledindex

Determine if e is a scaled index addressing mode.

int isscaledindex(
  uint ty,
  elem* e
) nothrow @trusted;

size S extend 0 0 UXTW *(int*)((char*)p + u); 0 0 LSL *(int*)((char*)p + l) 0 0 SXTW *(int*)((char*)p + i); 0 0 SXTX 0 1 UXTW #2 *(int*)((char*)p + u*4) 0 1 LSL #2 *(int*)((char*)p + l*4) 0 1 SXTW #2 *(int*)((char*)p + i*4) 0 1 SXTX #2 1 0 UXTW *(long*)((char*)p + u) 1 0 LSL *(long*)((char*)p + l) 1 0 SXTW *(long*)((char*)p + i) 1 0 SXTX 1 1 UXTW #3 *(long*)((char*)p + u*8) 1 1 LSL #3 *(long*)((char*)p + l*8) 1 1 SXTW #3 *(long*)((char*)p + i*8) 1 1 SXTX #3

Or

SXTB unsigned = FALSE; len = 8; SXTH unsigned = FALSE; len = 16; SXTW unsigned = FALSE; len = 32; SXTX unsigned = FALSE; len = 64; UXTB unsigned = TRUE; len = 8; UXTH unsigned = TRUE; len = 16; UXTW unsigned = TRUE; len = 32; UXTX unsigned = TRUE; len = 64;

References

https

//stackoverflow.com/questions/72041372/what-do-the-uxtx-and-sxtx-extensions-mean-for-32-bit-aarch64-adds-instruct

https

//www.scs.stanford.edu/~zyedidia/arm64/ldr_reg_gen.html

https

//www.scs.stanford.edu/~zyedidia/arm64/shared_pseudocode.html#impl-aarch64.ExtendReg.4

Returns

0 not a scaled index addressing mode !=0 the scaling shift count

Authors

Walter Bright

License

Boost License 1.0