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core.cpuid
Identify the characteristics of the host CPU, providing information
about cache sizes and assembly optimisation hints. This module is
provided primarily for assembly language programmers.
References Some of this information was extremely difficult to track down. Some of the documents below were found only in cached versions stored by search engines! This code relies on information found in:
- "Intel(R) 64 and IA-32 Architectures Software Developers Manual, Volume 2A: Instruction Set Reference, A-M" (2007).
- "AMD CPUID Specification", Advanced Micro Devices, Rev 2.28 (2008).
- "AMD Processor Recognition Application Note For Processors Prior to AMD Family 0Fh Processors", Advanced Micro Devices, Rev 3.13 (2005).
- "AMD Geode(TM) GX Processors Data Book", Advanced Micro Devices, Publication ID 31505E, (2005).
- "AMD K6 Processor Code Optimisation", Advanced Micro Devices, Rev D (2000).
- "Application note 106: Software Customization for the 6x86 Family", Cyrix Corporation, Rev 1.5 (1998)
- http://www.datasheetcatalog.org/datasheet/nationalsemiconductor/GX1.pdf
- "Geode(TM) GX1 Processor Series Low Power Integrated X86 Solution", National Semiconductor, (2002)
- "The VIA Isaiah Architecture", G. Glenn Henry, Centaur Technology, Inc (2008).
- http://www.sandpile.org/ia32/cpuid.htm
- http://www.akkadia.org/drepper/cpumemory.pdf
- "What every programmer should know about memory", Ulrich Depper, Red Hat, Inc., (2007).
- "CPU Identification by the Windows Kernel", G. Chappell (2009). http://www.geoffchappell.com/viewer.htm?doc=studies/windows/km/cpu/cx8.htm
- "Intel(R) Processor Identification and the CPUID Instruction, Application Note 485" (2009).
Bugs:
Currently only works on x86 and Itanium CPUs.
Many processors have bugs in their microcode for the CPUID instruction,
so sometimes the cache information may be incorrect.
License:
Authors:
Don Clugston, Tomas Lindquist Olsen <tomas@famolsen.dk>
Source core/cpuid.d
- struct
CacheInfo
; - Cache size and behaviour
- size_t
size
; - Size of the cache, in kilobytes, per CPU. For L1 unified (data + code) caches, this size is half the physical size. (we don't halve it for larger sizes, since normally data size is much greater than code size for critical loops).
- ubyte
associativity
; - Number of ways of associativity, eg:
- 1 = direct mapped
- 2 = 2-way set associative
- 3 = 3-way set associative
- ubyte.max = fully associative
- uint
lineSize
; - Number of bytes read into the cache when a cache miss occurs.
- CacheInfo[5]
datacache
; - Scheduled for deprecation. Please use dataCaches instead.
- pure nothrow @nogc @property @trusted const(CacheInfo)[5]
dataCaches
(); - The data caches. If there are fewer than 5 physical caches levels, the remaining levels are set to size_t.max (== entire memory space)
- pure nothrow @nogc @property @trusted string
vendor
(); - Returns vendor string, for display purposes only. Do NOT use this to determine features! Note that some CPUs have programmable vendorIDs.
- pure nothrow @nogc @property @trusted string
processor
(); - Returns processor string, for display purposes only
- pure nothrow @nogc @property @trusted bool
x87onChip
(); - Does it have an x87 FPU on-chip?
- pure nothrow @nogc @property @trusted bool
mmx
(); - Is MMX supported?
- pure nothrow @nogc @property @trusted bool
sse
(); - Is SSE supported?
- pure nothrow @nogc @property @trusted bool
sse2
(); - Is SSE2 supported?
- pure nothrow @nogc @property @trusted bool
sse3
(); - Is SSE3 supported?
- pure nothrow @nogc @property @trusted bool
ssse3
(); - Is SSSE3 supported?
- pure nothrow @nogc @property @trusted bool
sse41
(); - Is SSE4.1 supported?
- pure nothrow @nogc @property @trusted bool
sse42
(); - Is SSE4.2 supported?
- pure nothrow @nogc @property @trusted bool
sse4a
(); - Is SSE4a supported?
- pure nothrow @nogc @property @trusted bool
aes
(); - Is AES supported
- pure nothrow @nogc @property @trusted bool
hasPclmulqdq
(); - Is pclmulqdq supported
- pure nothrow @nogc @property @trusted bool
hasRdrand
(); - Is rdrand supported
- pure nothrow @nogc @property @trusted bool
avx
(); - Is AVX supported
- pure nothrow @nogc @property @trusted bool
vaes
(); - Is VEX-Encoded AES supported
- pure nothrow @nogc @property @trusted bool
hasVpclmulqdq
(); - Is vpclmulqdq supported
- pure nothrow @nogc @property @trusted bool
fma
(); - Is FMA supported
- pure nothrow @nogc @property @trusted bool
fp16c
(); - Is FP16C supported
- pure nothrow @nogc @property @trusted bool
avx2
(); - Is AVX2 supported
- pure nothrow @nogc @property @trusted bool
hle
(); - Is HLE (hardware lock elision) supported
- pure nothrow @nogc @property @trusted bool
rtm
(); - Is RTM (restricted transactional memory) supported
- pure nothrow @nogc @property @trusted bool
avx512f
(); - Is AVX512F supported
- pure nothrow @nogc @property @trusted bool
hasRdseed
(); - Is rdseed supported
- pure nothrow @nogc @property @trusted bool
hasSha
(); - Is SHA supported
- pure nothrow @nogc @property @trusted bool
amd3dnow
(); - Is AMD 3DNOW supported?
- pure nothrow @nogc @property @trusted bool
amd3dnowExt
(); - Is AMD 3DNOW Ext supported?
- pure nothrow @nogc @property @trusted bool
amdMmx
(); - Are AMD extensions to MMX supported?
- pure nothrow @nogc @property @trusted bool
hasFxsr
(); - Is fxsave/fxrstor supported?
- pure nothrow @nogc @property @trusted bool
hasCmov
(); - Is cmov supported?
- pure nothrow @nogc @property @trusted bool
hasRdtsc
(); - Is rdtsc supported?
- pure nothrow @nogc @property @trusted bool
hasCmpxchg8b
(); - Is cmpxchg8b supported?
- pure nothrow @nogc @property @trusted bool
hasCmpxchg16b
(); - Is cmpxchg8b supported?
- pure nothrow @nogc @property @trusted bool
hasSysEnterSysExit
(); - Is SYSENTER/SYSEXIT supported?
- pure nothrow @nogc @property @trusted bool
has3dnowPrefetch
(); - Is 3DNow prefetch supported?
- pure nothrow @nogc @property @trusted bool
hasLahfSahf
(); - Are LAHF and SAHF supported in 64-bit mode?
- pure nothrow @nogc @property @trusted bool
hasPopcnt
(); - Is POPCNT supported?
- pure nothrow @nogc @property @trusted bool
hasLzcnt
(); - Is LZCNT supported?
- pure nothrow @nogc @property @trusted bool
isX86_64
(); - Is this an Intel64 or AMD 64?
- pure nothrow @nogc @property @trusted bool
isItanium
(); - Is this an IA64 (Itanium) processor?
- pure nothrow @nogc @property @trusted bool
hyperThreading
(); - Is hyperthreading supported?
- pure nothrow @nogc @property @trusted uint
threadsPerCPU
(); - Returns number of threads per CPU
- pure nothrow @nogc @property @trusted uint
coresPerCPU
(); - Returns number of cores in CPU
- pure nothrow @nogc @property @trusted bool
preferAthlon
(); - Optimisation hints for assembly code.For forward compatibility, the CPU is compared against different microarchitectures. For 32-bit x86, comparisons are made against the Intel PPro/PII/PIII/PM family. The major 32-bit x86 microarchitecture 'dynasties' have been:
- Intel P6 (PentiumPro, PII, PIII, PM, Core, Core2).
- AMD Athlon (K7, K8, K10).
- Intel NetBurst (Pentium 4, Pentium D).
- In-order Pentium (Pentium1, PMMX, Atom)
- Intel Atom 230/330 (family 6, model 0x1C) is an in-order core.
- Centaur Isiah = VIA Nano (family 6, model F) is an out-of-order core.
- pure nothrow @nogc @property @trusted bool
preferPentium4
(); - Does this CPU perform better on Pentium4 code than PentiumPro..Core2 code?
- pure nothrow @nogc @property @trusted bool
preferPentium1
(); - Does this CPU perform better on Pentium I code than Pentium Pro code?
- uint
stepping
; - Warning: This field will be turned into a property in a future release.Processor type (vendor-dependent). This should be visible ONLY for display purposes.
- uint
model
; - Warning: This field will be turned into a property in a future release.Processor type (vendor-dependent). This should be visible ONLY for display purposes.
- uint
family
; - Warning: This field will be turned into a property in a future release.Processor type (vendor-dependent). This should be visible ONLY for display purposes.
- uint
numCacheLevels
; - This field has been deprecated. Please use cacheLevels instead.
- nothrow @nogc @property @trusted uint
cacheLevels
(); - The number of cache levels in the CPU.
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